1. Field of the Invention
The present invention relates to a method for fabricating a semiconductor device; and more particularly, to a method for fabricating a plurality of contact plugs capable of preventing a self-aligned contact (SAC) fail during forming a plurality of contact holes formed by using a SAC etching process and a defect generation during performing a plug isolation process.
2. Description of Related Arts
In general, a semiconductor device is comprised of a plurality of unit pixels inside of the semiconductor device. A trend in a large-scale of integration has brought a need to form semiconductor devices densely within a confined cell region. Thus, the size of unit devices of a semiconductor device, for instance, transistors and capacitors, has been gradually decreased. Particularly, in a dynamic random access memory (DRAM) device, the size of the unit devices formed within a cell region has been decreased as the design rule has been shifted towards minimization. For instance, DRAM devices are currently formed to have a minimum linewidth less than 0.1 μm and are often required to have a linewidth less than 80 nm. Hence, there exist many difficulties in applying conventional fabrication methods.
In case of applying a photolithography using ArF having a wavelength of 193 nm to a semiconductor device having a linewidth less than 80 nm, it is necessary to develop an additional recipe for preventing a photoresist deformation created during an etching process employed for the purposes of forming a fine pattern and a vertical etch profile. Accordingly, when fabricating the semiconductor device having a linewidth less than 80 nm, a conventional requirement for etching and a new requirement for preventing a pattern deformation should be simultaneously satisfied.
Meanwhile, advancement in an integration level of a semiconductor device has led device elements to be formed in stacks. A contact plug or a contact pad is one example of such stack structure.
For the contact plug, a landing plug contact (LPC) is commonly used since the LPC has a bottom portion which makes a wide contact within a minimum area and a top portion which is wider than the bottom portion for increasing a contact margin.
Furthermore, for forming such a LPC, there is a difficulty of etching between structures having a high aspect ratio. At this time, a self-aligned contact (SAC) etching process obtaining an etch profile by using an etch selectivity ratio of two materials, e.g., an oxide layer and a nitride layer is introduced.
For the SAC etching process, CF and CHF based gases are used, and it is also necessary to have an etch stop layer using a nitride layer for the purpose of preventing an attack to a conductive pattern of a lower portion or a spacer.
Hereinafter, a process forming a plurality of cell contacts by using the SAC etching process will be explained. FIGS. 1A to 1D are cross sectional views illustrating a conventional process forming a plurality of cell contacts.
First, referring to FIG. 1A, a plurality of gate electrode patterns G1 and G2 is formed on a substrate 100 provided with various device elements, i.e., a field insulation layer and a well (not shown) for forming a semiconductor device. Herein, each of the plurality of gate electrode patterns G1 and G2 is formed by stacking a gate conductive layer 101 and a hard mask on the substrate 100.
A gate insulation layer exists between the gate conductive layer 101 and the substrate 100 and uses a typical oxide-based layer such as a silicon oxide layer; however, herein, the gate insulation is omitted.
The gate conductive layer 101 is made of a material selected from a group consisting of polysilicon, tungsten (W), tungsten nitride (WNx), tungsten silicide (WSix). Also, it is possible to form the gate conductive layer 101 by using a material combining all of the above listed materials.
The gate hard mask 102 serves a role in protecting the gate conductive layer 101 in the course of an etching process for forming a plurality of contact holes by etching an inter-layer insulation layer. The gate hard mask 102 is made of a material having a different etching speed from the inter-layer insulation layer. For instance, in case of using an oxide-based layer for forming the inter-layer insulation layer, a nitride-based layer such as a silicon nitride (SiN) layer or a silicon oxynitirde (SiON) layer is used and in case of using a polymer based low k-dielectric layer for forming the inter-layer insulation layer, an oxide-based layer is used.
An impurity diffusion region (not shown) such as a source/drain junction is formed on the substrate 100 between the plurality of gate electrode patterns G1 and G2.
A spacer (not shown) is formed along a profile formed with the plurality of gate electrode patterns G1 and G2 and then, an etch stop layer 103 is formed to prevent an attack on lower structures such as the spacer and the plurality of gate electrode patterns G1 and G2 from the etching process by employing a subsequent SAC etching method on the above resulting substrate. At this time, it is preferable to form the etch stop layer 103 along the profile of the lower structures. The etch stop layer 103 uses a nitride-based layer.
Subsequently, an oxide-based inter-layer insulation layer 104 is formed on the above resulting substrate provided with the etch stop layer 103.
In case of using an oxide-based layer for forming the inter-layer insulation layer 104, a material selected from a group consisting of a boro-silicate-glass (BSG) layer, a boro-phospho-silicate-glass (BPSG) layer, a phospho-silicate-glass (PSG) layer, a tetra-ethyl-ortho-silicate (TEOS) layer, a high density plasma (HDP) oxide layer, a spin-on-glass (SOG) layer and an advanced planarization layer (APL) is used. Also, it is possible to use an inorganic or organic based low k-dielectric layer to form the inter-layer insulation layer.
Subsequently, the inter-layer insulation layer 104 is planarized by employing a chemical mechanical polishing (CMP) process and then, a nitride layer 105A for forming a sacrificial hard mask is formed on the inter-layer insulation layer 104.
The nitride layer 105A for forming the sacrificial hard mask is patterned by a subsequent process for securing an etching tolerance of a photoresist due to a limitation of a resolution in the course of performing a photolithography process and preventing a pattern deformation.
Subsequently, a photoresist pattern for forming a plurality of cell contact plugs is formed on the nitride layer 105A for forming the sacrificial hard mask.
Meanwhile, during forming the photoresist pattern 106, an anti-reflective coating layer can be used between the photoresist pattern and a lower structure of the photoresist pattern for the purpose of preventing an undesirable pattern formation from a scattered reflection due to a high degree of light reflection during a photo-exposure for a pattern formation and improving an adhesiveness between the photoresist pattern and the lower structure of the photoresist pattern. At this time, the anti-reflective coating layer mainly uses an organic based material having a similar etching property with the photoresist pattern. However, according to a process, the anti-reflective coating layer can be omitted.
More specific to the process for forming the photoresist pattern, a photoresist for ArF or F2 light source, e.g., COMA or acrylaid which is the photoresist for ArF light source, is coated on the lower structure of the anti-reflective coating layer or the nitride layer 105A for forming the sacrificial hard mask in a predetermined thickness by performing a spin coating method. Afterwards, predetermined portions of the photoresist are selectively photo-exposed by using ArF or F2 light source and a predecided reticle (not shown) for defining a width of a contact hole. Thereafter, a developing process proceeds by making a photo-exposed portion or a non-photo-exposed portion remain, and a cleaning process is then performed to remove etch remnants, thereby forming the photoresist pattern 106 which is a cell contact open mask. Herein, the photoresist pattern 106 is an I-type.
Next, referring to FIG. 1B, a sacrificial hard mask 105B defining a region where the cell contact plug is formed by etching the nitride layer 105A for forming the sacrificial hard mask with use of the photoresist pattern 106 as an etch mask.
Subsequently, the photoresist pattern 106 is removed by performing a photoresist stripping process. In case of using an organic based anti-reflective coating layer, the photoresist pattern is removed in the course of the photoresist stripping process.
Next, the inter-layer insulation layer 104 is subject to the SAC etching process by using the sacrificial hard mask 105B as an etch mask, thereby forming a plurality of contact holes exposing the etch stop layer 103 between the gate electrode patterns G1 and G2.
At this time, a typical recipe for the SAC etching process is employed. That is, a fluoride based plasma, e.g., CxFy (x and y range from approximately 1 to approximately 10) gas such as C2F4, C2F6, C3F8, C4F6, C5F8 or C5F10, is used as a main etch gas along with an additional CaHbFc (a,b and c range from approximately 1 to approximately 10) gas such as CH2F2, C3HF5 or CHF3. At this time, an inert gas such as He, Ne, Ar or Xe is used as a carrier gas.
Subsequently, an oxide-based capping layer having a poor step coverage such as an undoped-silicate-glass (USG) layer is deposited. Afterwards, the etch stop layer 103 is removed on lower portions of the plurality of contact holes by using a blanket-etch process, thereby opening the substrate 100 placed in the lower portions of the plurality of contact holes 107, i.e., the impurity diffusion region of the substrate 100.
At this time, the capping layer is formed for the purpose of protecting the hard mask 102 existing upper portion of the plurality of gate electrode patterns G1 and G2 during an opening process performed in the lower portions of the plurality of contact holes 107.
Next, etch remnants and by-products are removed by employing the cleaning process.
Referring to FIG. 1C, a conductive layer 108A for forming a plurality of plugs is deposited in a structure where the lower portions of the plurality of contact holes 107 are opened, thereby filling the plurality of contact holes 107 sufficiently.
The conductive layer 108A for forming the plurality of plugs is mainly made of a polysilicon layer.
Subsequently, a planarization process is performed to expose the gate hard mask 102, thereby forming a plurality of plugs 108B electrically connected with the impurity diffusion region of the substrate through the plurality of contact holes 107 and planarized with the gate hard mask 102. The CMP process is employed during the planarization process performed for isolating the plurality of plugs 108B.
Referring to FIG. 1D, since the nitride-based gate hard mask 102 and the plurality of plugs 108B made of polysilicon has a different polishing ratio from each other, there generates a height difference denoted with a reference denotation A between the gate hard mask 102 and the plurality of plugs 108B.
Furthermore, there generates another height difference denoted with a reference denotation B due to a different etch selectivity of the gate hard mask 102 and the inter-layer insulation layer 104 during a subsequent cleaning process performed for removing a defect generated during the CMP process.
The semiconductor device with a linewidth equal to or less than approximately 100 nm using the described plug forming technology uses the I-type photoresist pattern during forming the plurality of cell contact plugs and employs the CMP process when isolating the plurality of cell contact plugs into a cell contact plug for forming a bit line contact and a cell contact plug for forming a storage node contact.
The CMP process for isolating the plurality of plugs provides an advantage in effectively isolating a material layer consisting of more than three different layers such as a nitride layer, an oxide layer and polysilicon. However, there are following disadvantages.
First, it is very difficult to remove scratches caused by slurry particles and Pinocchio particles. These particles are decreased through a subsequent cleaning process; however, it is impossible to completely remove the defect, thereby degrading a quality of the semiconductor device and yields of products.
Secondly, as excessively polishing to isolate the plurality of plugs into the plug for forming the bit line contact and the plug for forming the storage node contact, there is a height difference of approximately 350 Å between the gate electrode patterns, i.e., between a word line hard mask and a cell contact plug and thus, an additional CMP process subjected to the oxide-based inter-layer insulation layer is necessary to remove the height difference.
Thirdly, since the polishing ratio of the CMP process is larger in an edge region of a wafer than a central region of the wafer, there is a problem of abruptly decreasing a height of the hard mask in the edge region of the wafer.
Fourthly, since the CMP process has a different polishing ratio depending on a density of a pattern, an excessive CMP process is required to overcome a difficulty in isolating a mat edge region where a cell region and a peripheral region meet each other, thereby causing non-uniformity of the gate hard mask.
Accordingly, it is required to develop a process technology for settle the above problems caused during the plug isolation.